With increased levels of integration in silicon devices, it is now possible to have several central processing unit (CPU) cores, peripherals and memory subsystems in a single integrated device. These devices are called systems on a chip (SoC). Due to the complexity of the architecture and the device, it is not possible for the silicon designers to verify and validate the device without knowledge of the end application. The impact of not having a first-pass functional device can be extremely costly.
These costs include: the cost of processed wafers; the turnaround time in identifying a bug; the work in releasing a new silicon sample; and lost customer opportunities due to short time windows. Thus completing both verification and validation on the device before it has been committed to tape-out is mandatory.
Verification determines if the system being built matches the specifications by comparing system results to a model of correctness. Coverage-driven verification ensures the functional requirements of the specification are correct and the behavior described is complete and consistent.
Validation determines if the system being built is what is desired by comparing system results to end-customer requirements. Validation exerts influence over both the beginning and the end of the design cycle. Initially high level system models are validated. Later hardware accelerators are validated ensuring that the right system is being built.
The goals of any satisfactory verification and validation (V&V) are: a first pass functional device; the device works in the system for which it was developed; customer focus on value added work building on device capabilities and support software; not only composite device modules but also interactions between the modules under stress (maximum usage conditions) are validated.
Verification and validation has developed substantially since early work on general purpose processor devices. FIG. 1 illustrates an example of a conventional audio-video processor device. Central processing unit (CPU) 100 interfaces directly with program cache memory and data cache memory. Major blocks of the audio-video processor interface through switch fabric communication device 111. These blocks: include central processing unit 100; DSP co-processor 110; image processor 123; video port 101; memory interface 112; and peripheral interface 114. Each major block of the audio-video processor device of FIG. 1 is a megacell and each block separately receives conventional verification and validation. Blocks external to the audio-video processor include: image sensor 103; TV unit 104; liquid crystal display (LCD) 105; SD card 130; and audio codec 131. FIG. 1 also illustrates video port buffers 102, image processor DMA 124 and image buffer unit 125.
FIG. 2 illustrates a flow chart of a conventional verification and validation on the audio-video processor device of FIG. 1. Step 201 defines test matrices. These test matrices detail in table form all of the combinations of test conditions and input signals valid for each megacell simulation. Step 202 develops test cases to be covered by the megacell simulations for these test matrices. Step 203 simulates a RTL model for each megacell. Step 204 simulates a gate level model for each megacell.
Step 205 develops a gate level model for the entire chip by compiling the gate level models of the magacells. Step 206 develops test patterns for the entire chip. Step 207 simulates an RTL model of the entire chip in parallel with step 208 which simulates a gate level model of the entire chip. Step 209 compare results of the gate-level model simulation of step 207 and the RTL model simulation or 208. Step 210 fixes bugs identified by comparison 209.